This invention relates in general to voltage controlled oscillators and in particular, to voltage controlled oscillators including one or more voltage controlled delay circuits with power supply noise isolation.
Power supply noise may be a significant problem in mixed-mode circuits including both digital and analog circuitry on the same integrated circuit chip. In such mixed-mode circuits, noise induced on a power supply line by the switching of the digital circuitry may cause the analog circuitry connected to the power supply line to perform poorly or inaccurately. The performance of certain analog circuitry such as voltage controlled delay elements and voltage controlled oscillators including a ring oscillator formed of such voltage controlled delay elements are particularly sensitive to such noise.
FIG. 1 illustrates, as an example, a prior art voltage controlled oscillator ("VCO") 20. Included in the VCO 20 are a plurality of current controlled delay cells, 25-1 to 25-k, connected together to form a k-stage ring oscillator, wherein an input of each current controlled delay cell (or stage) in the ring oscillator is connected to an output of another current controlled delay cell in the ring oscillator. For example, an input in-2 of a second current controlled delay cell 25-2 is shown connected to an output out-1 of a first current controlled delay cell 25-1 in the ring oscillator, and as another example, an input in-1 of the first current controlled delay cell 25-1 is shown connected to an output out-k of a last current controlled delay cell 25-k in the ring oscillator.
Also included in the VCO 20 is a p-mos transistor 24, an n-mos transistor 21, and a resistor 23 connected together to form a controllable current sink, and a plurality of p-mos transistors, 26-1 to 26-k, individually connected to the p-mos transistor 24 to form a plurality of current mirrors. The p-mos transistor 24 is a diode-connected transistor having its source connected to a high voltage end Vdd of a power supply, and its gate and drain connected together. The n-mos transistor 21 acts as a control transistor having its source connected through the resistor 23 to a ground reference Gnd, and its drain connected through the diode-connected p-mos transistor 24 to the high voltage end Vdd of the power supply, such that a control voltage Vcnt applied to the gate of the n-mos transistor 21 controls a current Icnt flowing through the diode-connected p-mos transistor 24, the n-mos transistor 21, and the resistor 23. The sources of each of the p-mos transistors, 26-1 to 26-k, is connected to the supply voltage Vdd, and the gates of each of the p-mos transistors, 26-1 to 26-k, is connected to the gate of the p-mos transistor 24, such that a current flowing through each of the plurality of p-mos transistors, 26-1 to 26-k, mirrors the control current Icnt. Accordingly, the control voltage Vcnt applied to the gate of the n-mos transistor 21 controls the period of oscillation of the VCO 20 by controlling the current flowing into each of the current controlled delay cells, 25-1 to 25-k, which in turn, controls the delay of each of the current controlled delay cells, 25-1 to 25-k, which in turn, determines the period of oscillation of the VCO 20.
One problem with the prior art VCO 20, however, is that noise on a power supply line connected to the high voltage end Vdd of the power supply is readily transmitted through the plurality of p-mos transistors, 26-1 to 26-k, and as a consequence, readily transmitted as current fluctuations flowing into the plurality of current controlled delay cells, 25-1 to 25-k. This results in the period of oscillation of the VCO 20 inadvertently fluctuating from its intended controlled state.